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19-0094; Rev 11; 8/08
Microprocessor Supervisory Circuits
General Description
The MAX691A/MAX693A/MAX800L/MAX800M microprocessor (P) supervisory circuits are pin-compatible upgrades to the MAX691, MAX693, and MAX695. They improve performance with 30A supply current, 200ms typ reset active delay on power-up, and 6ns chipenable propagation delay. Features include write protection of CMOS RAM or EEPROM, separate watchdog outputs, backup-battery switchover, and a RESET output that is valid with VCC down to 1V. The MAX691A/ MAX800L have a 4.65V typical reset-threshold voltage, and the MAX693A/MAX800Ms' reset threshold is 4.4V typical. The MAX800L/MAX800M guarantee power-fail accuracies to 2%.
____________________________Features
o 200ms Power-OK/Reset Timeout Period o 1A Standby Current, 30A Operating Current o On-Board Gating of Chip-Enable Signals, 10ns max Delay o MaxCap(R) or SuperCap Compatible o Guaranteed RESET Assertion to VCC = +1V o Voltage Monitor for Power-Fail or Low-Battery Warning o Power-Fail Accuracy Guaranteed to 2% (MAX800L/M) o Available in 16-Pin Narrow SO, Plastic DIP, and TSSOP Packages
MAX691A/MAX693A/MAX800L/MAX800M
________________________Applications
Computers Controllers Intelligent Instruments Automotive Systems Critical P Power Monitoring
PART MAX691ACUE MAX691ACSE MAX691ACWE MAX691ACPE MAX691AC/D MAX691AEUE MAX691AESE
0.1F
Ordering Information
TEMP RANGE -0C to +70C -0C to +70C -0C to +70C -0C to +70C -0C to +70C -0C to +70C -40C to +85C -40C to +85C -40C to +85C PINPACKAGE 16 TSSOP 16 Narrow SO 16 Wide SO 16 Plastic DIP Dice* 16 TSSOP 16 Narrow SO 16 Wide SO 16 Plastic DIP
Typical Operating Circuit
+8V 5V REGULATOR
MAX691AEWE MAX691AEPE
1N4148 1 0.47F*
3 VCC VBATT
5 BATT ON
VOUT CE OUT
2 12 CMOS RAM
Ordering Information continued on last page. *Dice are specified at TA = +25C, DC parameters only. Devices in PDIP, SO, and TSSOP packages are available in both leaded and lead-free packaging. Specify lead free by adding the + symbol at the end of the part number when ordering. Lead free not available for CERDIP package.
ADDRESS DECODE
TOP VIEW
MAX691A 9 MAX693A CE IN 13 PFI MAX800L MAX800M
4 7 NO CONNECTION 8 GND WDI OSC IN PFO 10 OSC SEL LOW LINE WDO 6 14 *MaxCap RESET 15 11
Pin Configuration
A0-A15 I/O
VBATT 1 VOUT 2 VCC 3 GND 4 BATT ON 5 LOW LINE 6 16 RESET 15 RESET 14 WDO
P
NMI RESET AUDIBLE ALARM
MAX691A MAX693A MAX800L MAX800M
13 CE IN 12 CE OUT 11 WDI 10 PFO 9 PFI
OSC IN 7 OSC SEL 8
SYSTEM STATUS INDICATORS
DIP/SO/TSSOP
MaxCap is a registered trademark of Kanthal Globar, Inc.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Microprocessor Supervisory Circuits MAX691A/MAX693A/MAX800L/MAX800M
ABSOLUTE MAXIMUM RATINGS
Terminal Voltage (with respect to GND) VCC .......................................................................-0.3V to +6V VBATT...................................................................-0.3V to +6V All Other Inputs .....................................-0.3V to (VOUT + 0.3V) Input Current VCC Peak...........................................................................1.0A VCC Continuous.............................................................250mA VBATT Peak ..................................................................250mA VBATT Continuous ..........................................................25mA GND, BATT ON .............................................................100mA All Other Outputs ............................................................25mA Continuous Power Dissipation (TA = +70C) TSSOP (derate 6.70mW/C above +70C) ..................533mW Narrow SO (derate 8.70mW/C above +70C) ...........696mW Wide SO (derate 9.52mW/C above +70C)...............762mW Plastic DIP (derate 10.53mW/C above +70C) ..........842mW CERDIP (derate 10.00mW/C above +70C) ..............800mW Operating Temperature Ranges MAX69_AC_ _/MAX800_C_ _ .............................0C to +70C MAX69_AE_ _/MAX800_E_ _ ...........................-40C to +85C MAX69_AMJE ................................................-55C to +125C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(MAX691A, MAX800L: VCC = +4.75V to +5.5V; MAX693A, MAX800M: VCC = +4.5V to +5.5V; VBATT = 2.8V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX UNITS Operating Voltage Range, VCC, VBATT (Note 1) IOUT = 25mA MAX69_AC VOUT Output VCC = 4.5V IOUT = 250mA MAX69_AE, MAX800_C/E MAX69_A/M IOUT = 210mA MAX69_AC/AE, MAX800_C/E VCC - 0.17 0.8 0.8 0.8 VBATT - 0.3 VBATT - 0.25 VBATT - 0.15 15 25 30 30 0.04 100 1 A 5 -0.1 -1.0 VBATT + 0.3 VBATT - 0.3 0.02 0.02 A V 0 VCC - 0.02 VCC - 0.2 VCC - 0.2 5.5 VCC - 0.05 VCC - 0.3 VCC - 0.35 VCC - 0.40 VCC - 0.3V 1.2 1.4 1.6 V V V
MAX69_AC, MAX800_C VCC-to-VOUT On-Resistance VCC = 4.5V MAX69_AE, MAX800_E
VOUT in Battery-Backup Mode VBATT-to-VOUT On-Resistance Supply Current in Normal Operating Mode (excludes IOUT) Supply Current in Battery-Backup Mode (excludes IOUT) (Note 2) VBATT Standby Current (Note 3) Battery Switchover Threshold 2
MAX69_A/M VBATT = 4.5V, IOUT = 20mA VBATT = 2.8V, IOUT = 10mA VBATT = 2.0V, IOUT = 5mA VBATT = 4.5V VBATT = 2.8V VBATT = 2.0V VCC > VBATT - 1V VCC < VBATT - 1.2V, TA = +25C VBATT = 2.8V TA = TMIN + TMIN VBATT + 0.2V VCC Power-up Power-down TA = +25C TA = TMIN + TMIN
A
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Microprocessor Supervisory Circuits
ELECTRICAL CHARACTERISTICS (continued)
(MAX691A, MAX800L: VCC = +4.75V to +5.5V; MAX693A, MAX800M: VCC = +4.5V to +5.5V; VBATT = 2.8V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER Battery Switchover Hysteresis BATT ON Output Low Voltage BATT ON Output Short-Circuit Current ISINK = 3.2mA ISINK = 25mA Sink current Source current CONDITIONS MIN TYP 60 0.1 0.7 60 15 4.65 4.40 0.4 1.5 100 4.75 4.50 4.70 4.45 15 Power-down 80 800 140 200 2048 1.0 70 1.6 100 4096 1024 2.25 140 280 mV s ns ms Clock Cycles sec ms Clock Cycles ns 0.004 0.1 3.5 7 0.1 0.4 0.4 3.5 1 15 100 0.4 3.5 3 0.75 x VCC 0.8 -50 -10 20 50 10 20 mA V V A V mA V A 3 0.3 0.4 V MAX UNITS mV V mA A
MAX691A/MAX693A/MAX800L/MAX800M
1 4.50 4.25 4.55 4.30
RESET AND WATCHDOG TIMER MAX691A, MAX800L Reset Threshold Voltage MAX693A, MAX800M MAX800L, TA = +25C, VCC falling MAX800M, TA = +25C, VCC falling Reset Threshold Hysteresis VCC to RESET Delay LOW LINE-to-RESET Delay Reset Active Timeout Period, Power-up Internal Oscillator Reset Active Timeout Period, Power-up External Clock (Note 4) Watchdog Timeout Period, Internal Oscillator Watchdog Timeout Period, External Clock (Note 4) Minimum Watchdog Input Pulse Width RESET Output Voltage Long period Short period Long period Short period VIL = 0.8V, VIH = 0.75 x VCC ISINK = 50A, VCC = 1V, VBATT = 0V, VCC falling ISINK = 3.2mA, VCC = 4.25V ISOURCE = 1.6mA, VCC = 5V
100
V
- RESET Output Short-Circuit Output source current Current RESET Output Voltage Low ISINK = 3.2mA (Note 5) LOW LINE Output Voltage LOW LINE Output Short-Circuit Current WDO Output Voltage WDO Output Short-Circuit Current WDI Threshold Voltage (Note 6) WDI Input Current ISINK = 3.2mA, VCC = 4.25V ISOURCE = 1A, VCC = 5V Output source current ISINK = 3.2mA ISOURCE = 500A, VCC = 5V Output source current VIH VIL WDI = 0V WDI = VOUT
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Microprocessor Supervisory Circuits MAX691A/MAX693A/MAX800L/MAX800M
ELECTRICAL CHARACTERISTICS (continued)
(MAX691A, MAX800L: VCC = +4.75V to +5.5V; MAX693A, MAX800M: VCC = +4.5V to +5.5V; VBATT = 2.8V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER POWER-FAIL COMPARATOR PFI Input Threshold PFI Leakage Current PFO Output Voltage PFO Output Short-Circuit Current PFI-to-PFO Delay CHIP-ENABLE GATING CE IN Leakage Current CE IN-to-CE OUT Resistance (Note 7) CE OUT Short-Circuit Current (Reset Active) CE IN-to-CE OUT Propagation Delay (Note 8) CE OUT Output-Voltage High (Reset Active) RESET-to-CE OUT Delay INTERNAL OSCILLATOR OSC IN Leakage Current OSC IN Input Pullup Current OSC SEL Input Pullup Current OSC IN Frequency Range OSC IN External Oscillator Threshold Voltage OSC IN Frequency with External Capacitor OSC SEL = 0V OSC SEL = VOUT or floating, OSC IN = 0V OSC SEL = 0V OSC SEL = 0V VIH VIL OSC SEL = 0V, COSC = 47pF VOUT - 0.3 0.10 10 10 50 VOUT - 0.6 3.65 100 2.00 5 100 100 A A A kHz V kHz Disable mode Enable mode - Disable mode, CE OUT = 0V 50 source impedance driver, CLOAD = 50pF VCC = 5V, IOUT = -100A VCC = 0V, VBATT = 2.8V, IOUT = 1A Power-down 3.5 2.7 12 0.1 0.005 75 0.75 6 1 150 2.0 10 A mA ns V s ISINK = 3.2mA ISOURCE = 1A, VCC = 5V Output source current VIN = -20mV, VOD = 15mV VIN = 20mV, VOD = 15mV 3.5 1 15 25 60 100 MAX69_AC/AE/AM, VCC = 5V MAX800_C/E, VCC = 5V 1.2 1.225 1.25 1.25 0.01 1.3 1.275 25 0.4 V nA V A s CONDITIONS MIN TYP MAX UNITS
Note 1: Either VCC or VBATT can go to 0V, if the other is greater than 2.0V. Note 2: The supply current drawn by the MAX691A/MAX800L/MAX800M from the battery excluding IOUT typically goes to 10A when (VBATT - 1V) < VCC < VBATT. In most applications, this is a brief period as VCC falls through this region. Note 3: "+" = battery-discharging current, "--" = battery-charging current. Note 4: Although presented as typical values, the number of clock cycles for the reset and watchdog timeout periods are fixed and do not vary with process or temperature. Note 5: RESET is an open-drain output and sinks current only. Note 6: WDI is internally connected to a voltage divider between VOUT and GND. If unconnected, WDI is driven to 1.6V (typ), disabling the watchdog function. Note 7: The chip-enable resistance is tested with VCC = +4.75V for the MAX691A/MAX800L and VCC = +4.5V for the MAX693A/MAX800M. CE IN = CE OUT = VCC/2. Note 8: The chip-enable propagation delay is measured from the 50% point at CE IN to the 50% point at CE OUT. 4 _______________________________________________________________________________________
Microprocessor Supervisory Circuits
__________________________________________Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
VCC SUPPLY CURRENT vs. TEMPERATURE (NORMAL OPERATING MODE)
MAX691A TOC-01
MAX691A/MAX693A/MAX800L/MAX800M
BATTERY SUPPLY CURRENT vs. TEMPERATURE (BATTERY-BACKUP MODE)
MAX691A TOC-02
CHIP-ENABLE ON-RESISTANCE vs. TEMPERATURE
VCC = 4.75V VBATT = 2.8V VCE IN = VCC/2
MAX691A TOC-03
36 VCC = 5V VBATT = 2.8V PFI, CE IN = 0V
2 BATTERY SUPPLY CURRENT (A) VCC = 5V VBATT = 2.8V NO LOAD
120
VCC SUPPLY CURRENT (A)
34
32
1
CE ON-RESISTANCE ()
1.5
100
80
30
28
0.5
60
26 -60 -30 0 30 60 90 120 150 TEMPERATURE (C)
0 -60 -30 0 30 60 90 120 150 TEMPERATURE (C)
40 -60 -30 0 30 60 90 120 150 180 TEMPERATURE (C)
VBATT to VOUT ON-RESISTANCE vs. TEMPERATURE
MAX691A TOC-04
VCC to VOUT ON-RESISTANCE vs. TEMPERATURE
MAX691A TOC-05
PFI THRESHOLD vs. TEMPERATURE
MAX691A TOC-06
20 VBATT-to-VOUT ON-RESISTANCE ()
1.2 VCC-to-VOUT ON-RESISTANCE () 1.1 1.0 0.9 0.8 0.7 0.6
VCC = 5V, VBATT = 0V
1.50 1.25 PFI THRESHOLD (V) 1.00 0.75 0.50 0.25 0 VCC = +5V, VBATT = 0V NO LOAD ON PFO -60 -30 0 30 60 90 120
VBATT = 2.0V 15 VBATT = 2.8V 10 VBATT = 4.5V 5 -60 -30 0 30 60 90 TEMPERATURE (C) VCC = 0V 120 150
-60
-30
0
30
60
90
120
150
150
TEMPERATURE (C)
TEMPERATURE (C)
RESET THRESHOLD vs. TEMPERATURE
MAX691A TOC-07
RESET OUTPUT RESISTANCE vs. TEMPERATURE
MAX691A TOC-08
RESET DELAY vs. TEMPERATURE
VCC = 0V TO 5V STEP VBATT = 2.8V
MAX691A TOC-09
4.75 4.70 RESET THRESHOLD (V) 4.65 4.60 4.55 4.50 4.45 4.40 4.35 4.30
VBATT = 2.8V
600 RESET OUTPUT RESISTANCE () 500 400 300 200 100 0 VCC = 0V, VBATT = 2.8V SINKING CURRENT -60 -30 0 30 60 90 120
230 220 RESET DELAY (ms) 210 200 190 180 170
MAX691A MAX800L
VCC = 5V, VBATT = 2.8V SOURCING CURRENT
MAX693A MAX800M -60 -30 0 30 60 90 120 150
150
-60
-30
0
30
60
90
120
150
TEMPERATURE (C)
TEMPERATURE (C)
TEMPERATURE (C)
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Microprocessor Supervisory Circuits MAX691A/MAX693A/MAX800L/MAX800M
____________________________Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
BATTERY CURRENT vs. INPUT SUPPLY VOLTAGE
WATCHDOG AND RESET TIMEOUT PERIOD (sec)
MAX691A TOC-10
WATCHDOG AND RESET TIMEOUT PERIOD vs. OSC IN TIMING CAPACITOR (COSC)
MAX691A TOC-11
CHIP-ENABLE PROPAGATION DELAY vs. CE OUT LOAD CAPACITANCE
VCC = 5V CE IN = 0V TO 5V DRIVER SOURCE
MAX691A TOC-12
20
VBATT = 2.8V IOUT = 0A
100
VCC = 5V VBATT = 2.8V
20
LONG WATCHDOG TIMEOUT PERIOD
10 RESET ACTIVE TIMEOUT PERIOD
IBATT (A)
12
PROPAGATION DELAY (ns)
16
16
12
8
8
1 SHORT WATCHDOG TIMEOUT PERIOD
4
4
0 0 1 2 VCC (V) 3 4 5
0.1 10 100 COSC (pF) 1000
0 0 50 100 150 CLOAD (pF) 200 250 300
VCC to VOUT vs. OUTPUT CURRENT (NORMAL OPERATING MODE)
MAX691A TOC-13
VBATT to VOUT vs. OUTPUT CURRENT (BATTERY-BACKUP MODE)
VCC = 0V VBATT = 4.5V
MAX691A TOC-14
VCC to LOW LINE AND CE OUT DELAY
5V VCC RESET THRESHOLD 80s HI LOW LINE LO 800ns
MAX691A TOC-15
1000
VCC = 4.5V VBATT = 0V
1000
100
VBATT to VOUT (mV)
VCC to VOUT (mV)
100
10
SLOPE = 0.8
10
SLOPE = 8
HI RESET LO HI CE OUT 12s
1 1 10 IOUT (mA) 100 1000
1 1 10 IOUT (mA) 100
LO
6
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Microprocessor Supervisory Circuits
______________________________________________________________Pin Description
PIN 1 2 3 4 5 6 NAME VBATT VOUT VCC GND FUNCTION Battery-Backup Input. Connect to external battery or capacitor and charging circuit. If backup battery is not used, connect to GND. Output Supply Voltage. When VCC is greater than VBATT and above the reset threshold, VOUT connects to VCC. When VCC falls below VBATT and is below the reset threshold, VOUT connects to VBATT. Connect a 0.1F capacitor from VOUT to GND. Connect VOUT to VCC if no backup battery is used. Input Supply Voltage, 5V Input.
MAX691A/MAX693A/MAX800L/MAX800M
7
8 9 10
11
12 13 14 15 16
Ground. 0V reference for all signals. Battery-On Output. When VOUT switches to VBATT, BATT ON goes high. When VOUT switches to VCC, BATT ON BATT ON goes low. Connect the base of a PNP through a current-limiting resistor to BATT ON for VOUT current requirements greater than 250mA. LOW LINE output goes low when VCC falls below the reset threshold. It returns high as soon as VCC rises above LOW LINE the reset threshold. External Oscillator Input. When OSC SEL is unconnected or driven high, a 10A pull-up connects from VOUT to OSC IN, the internal oscillator sets the reset and watchdog timeout periods, and OSC IN selects between fast OSC IN and slow watchdog timeout periods. When OSC SEL is driven low, the reset and watchdog timeout periods may be set either by a capacitor from OSC IN to ground or by an external clock at OSC IN (Figure 3). Oscillator Select. When OSC SEL is unconnected or driven high, the internal oscillator sets the reset delay and OSC SEL watchdog timeout period. When OSC SEL is low, the external oscillator input (OSC IN) is enabled (Table 1). OSC SEL has a 10A internal pull-up. Power-Fail Input. This is the noninverting input to the power-fail comparator. When PFI is less than 1.25V, PFO PFI goes low. When PFI is not used, connect PFI to GND or VOUT . Power-Fail Output. This is the output of the power-fail comparator. PFO goes low when PFI is less than 1.25V. PFO This is an uncommitted comparator, and has no effect on any other internal circuitry. Watchdog Input. WDI is a three-level input. If WDI remains either high or low for longer than the watchdog timeout period, WDO goes low and reset is asserted for the reset timeout period. WDO remains low until the next tranWDI sition at WDI. Leaving WDI unconnected disables the watchdog function. WDI connects to an internal voltage divider between VOUT and GND, which sets it to mid-supply when left unconnected. Chip-Enable Output. CE OUT goes low only when CE IN is low and VCC is above the reset threshold. If CE IN is CE OUT low when reset is asserted, CE OUT will stay low for 15s or until CE IN goes high, whichever occurs first. CE IN Chip-Enable Input. The input to chip-enable gating circuit. If CE IN is not used, connect CE IN to GND or VOUT. Watchdog Output. If WDI remains high or low longer than the watchdog timeout period, WDO goes low and reset WDO is asserted for the reset timeout period. WDO returns high on the next transition at WDI. WDO remains high if WDI is unconnected. RESET Output goes low whenever VCC falls below the reset threshold. RESET will remain low typically for RESET 200ms after VCC crosses the reset threshold on power-up. RESET RESET is an active-high output. It is open drain, and the inverse of RESET.
_______________Detailed Description
--- -- - ---- R E S E T and RESET Outputs
The MAX691A/MAX693A/MAX800L/MAX800M's RESET and RESET outputs ensure that the P (with reset inputs asserted either high or low) powers up in a known state, and prevents code-execution errors during power-down or brownout conditions. The RESET output is active low, and typically sinks 3.2mA at 0.1V saturation voltage in its active state. - When deasserted, RESET sources 1.6mA at typically VOUT - 0.5V. RESET output is open drain, active high, and typically sinks 3.2mA with a saturation voltage of 0.1V. When no backup battery is used, RESET output is
guaranteed to be valid down to V CC = 1V, and an external 10k pulldown resistor on RESET insures that it will be valid with VCC down to GND (Figure 1). As VCC goes below 1V, the gate drive to the RESET output switch reduces accordingly, increasing the RDS(ON) and the saturation voltage. The 10k pulldown resistor insures the parallel combination of switch plus resistor is around 10k and the output saturation voltage is below 0.4V while sinking 40A. When using a 10k external pulldown resistor, the high state for RESET output with VCC = 4.75V will be 4.5V typical. For battery voltages 2V connected to VBATT, RESET and RESET remain valid for VCC from 0V to 5.5V.
7
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Microprocessor Supervisory Circuits MAX691A/MAX693A/MAX800L/MAX800M
WDI
RESET
15
TO P RESET 1k
WDO
MAX691A MAX693A
t2 RESET t1 t1 t3
t1 = RESET TIMEOUT PERIOD t2 = NORMAL WATCHDOG TIMEOUT PERIOD t3 = WATCHDOG TIMEOUT PERIOD IMMEDIATELY AFTER RESET
Figure 1. Adding an external pulldown resistor ensures ----- -- --- RESET is valid with VCC down to GND.
Figure 2. Watchdog Timeout Period and Reset Active Time
RESET and RESET are asserted when VCC falls below the reset threshold (4.65V for the MAX691A/MAX800L, 4.4V for the MAX693A/MAX800M) and remain asserted for 200ms typ after VCC rises above the reset threshold on power-up (Figure 5). The devices' batteryswitchover comparator does not affect reset assertion. However, both reset outputs are asserted in batterybackup mode since V CC must be below the reset threshold to enter this mode.
Watchdog Function
The watchdog monitors P activity via the Watchdog Input (WDI). If the P becomes inactive, RESET and RESET are asserted. To use the watchdog function, connect WDI to a bus line or P I/O line. If WDI remains high or low for longer than the watchdog timeout period (1.6s nominal), WDO, RESET, and RESET are asserted (see RESET and RESET Outputs section, and the Watchdog Output discussion on this page).
Watchdog Output The Watchdog Output (WDO) remains high if there is a transition or pulse at WDI during the watchdog timeout - period. The watchdog function is disabled and WDO is a logic high when VCC is below the reset threshold, battery-backup mode is enabled, or WDI is an open circuit. In watchdog mode, if no transition occurs at WDI during the watchdog timeout period, RESET and RESET are asserted for the reset timeout period (200ms typical). WDO goes low and remains low until the next transition at WDI (Figure 2). If WDI is held high or low indefinitely, RESET and RESET will generate 200ms pulses every 1.6s. WDO has a 2 x TTL output characteristic. Selecting an Alternative Watchdog and Reset Timeout Period The OSC SEL and OSC IN inputs control the watchdog and reset timeout periods. Floating OSC SEL and OSC IN or tying them both to VOUT selects the nominal 1.6s watchdog timeout period and 200ms reset timeout period. Connecting OSC IN to GND and floating or connecting OSC SEL to V OUT selects the 100ms normal watchdog timeout delay and 1.6s delay immediately after reset. The reset timeout delay remains 200ms (Figure 2). Select alternative timeout periods by connecting OSC SEL to GND and connecting a capacitor between OSC IN and GND, or by externally driving OSC IN (Table 1 and Figure 3). OSC IN is internally connected to a 100nA (typ) current source that charges and discharges the timing capacitor to create the oscillator frequency, which sets the reset and watchdog timeout periods (see Connecting a Timing Capacitor at OSC IN in the Applications Information section).
Watchdog Input A change of state (high to low, low to high, or a minimum 100ns pulse) at the WDI during the watchdog period resets the watchdog timer. The watchdog default timeout is 1.6s. To disable the watchdog function, leave WDI floating. An internal resistor network (100k equivalent impedance at WDI) biases WDI to approximately 1.6V. Internal comparators detect this level and disable the watchdog timer. When VCC is below the reset threshold, the watchdog function is disabled and WDI is disconnected from its internal resistor network, thus becoming high impedance.
8
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Microprocessor Supervisory Circuits MAX691A/MAX693A/MAX800L/MAX800M
Table 1. Reset Pulse Width and Watchdog Timeout Selections
OSC SEL Low Low Floating Floating OSC IN External Clock Input External Capacitor Low Floating Watchdog Timeout Period Normal 1024 clks (600/47pF x C)ms 100ms 1.6s Immediately After Reset 4096 clks (2.4/47pF x C)sec 1.6s 1.6s Reset Timeout Period 2048 clks (1200/47pF x C)ms 200ms 200ms
MAX691A MAX693A MAX800L MAX800M
50kHz
EXTERNAL CLOCK 8 OSC SEL 8 7
EXTERNAL OSCILLATOR OSC SEL OSC IN
7
OSC IN
INTERNAL OSCILLATOR 1.6s WATCHDOG N.C. N.C. 8 OSC SEL N.C.
INTERNAL OSCILLATOR 100ms WATCHDOG 8 OSC SEL
7
OSC IN
7
OSC IN
In the high-impedance mode, the leakage currents into this terminal are 1A max over temperature. In the - low-impedance mode, the impedance of CE IN appears as a 75 resistor in series with the load at CE OUT. The propagation delay through the CE transmission gate depends on both the source impedance of the - drive to CE IN and the capacitive loading on the Chip- Enable Output (CE OUT) (see Chip-Enable Propagation Delay vs. CE OUT Load Capacitance in the Typical Operating Characteristics). The CE propagation delay - is production tested from the 50% point of CE IN to the - 50% point of CE OUT using a 50 driver and 50pF of load capacitance (Figure 6). For minimum propagation delay, minimize the capacitive load at CE OUT, and use a low output-impedance driver.
Figure 3. Oscillator Circuits
Chip-Enable Signal Gating
The MAX691A/MAX693A/MAX800L/MAX800M provide internal gating of chip-enable (CE) signals to prevent erroneous data from being written to CMOS RAM in the event of a power failure. During normal operation, the CE gate is enabled and passes all CE transitions. When reset is asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. All - these parts use a series transmission gate from CE IN to CE OUT (Figure 4). The 10ns max CE propagation delay from CE IN to CE OUT enables the parts to be used with most Ps.
Chip-Enable Output In the enabled mode, the impedance of CE OUT is equivalent to 75 in series with the source driving CE IN. In the disabled mode, the 75 transmission gate is off and CE OUT is actively pulled to VOUT. This source turns off when the transmission gate is enabled.
- ------ -- -- ---- - LOW LINE Output
LOW LINE is the buffered output of the reset threshold comparator. LOW LINE typically sinks 3.2mA at 0.1V. For normal operation (VCC above the LOW LINE threshold), LOW LINE is pulled to VOUT.
Power-Fail Comparator
The power-fail comparator is an uncommitted comparator that has no effect on the other functions of the IC. Common uses include low-battery indication (Figure 7), and early power-fail warning (see Typical Operating Circuit).
Chip-Enable Input The Chip-Enable Input (CE IN) is high impedance (disabled mode) while RESET and RESET are asserted. During a power-down sequence where VCC falls below - the reset threshold or a watchdog fault, CE IN assumes a high-impedance state when the voltage at CE IN goes high or 15s after reset is asserted, whichever occurs first (Figure 5). During a power-up sequence, CE IN remains high impedance, regardless of CE IN activity, until reset is deasserted following the reset timeout period.
Power-Fail Input Power-Fail Input (PFI) is the input to the power-fail comparator. It has a guaranteed input leakage of 25nA max over temperature. The typical comparator delay is 25s from VIL to VOL (power failing), and 60s from VIH to VOH (power being restored). If PFI is not used, connect it to ground.
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9
Microprocessor Supervisory Circuits MAX691A/MAX693A/MAX800L/MAX800M
5 4.65V* 3 2 CHIP-ENABLE OUTPUT CONTROL 12 16 CE OUT RESET VOUT BATT ON 6
LOW LINE
VCC
VBATT CE IN
1 13
MAX691A MAX693A MAX800L MAX800M
OSC IN OSC SEL 7 8 TIMEBASE FOR RESET AND WATCHDOG WATCHDOG TRANSITION DETECTOR
RESET GENERATOR
15
RESET
WDI PFI
11 9
WATCHDOG TIMER
14 10
WDO PFO
1.25V
4 GND * 4.4V FOR THE MAX693A/MAX800M
Figure 4. MAX691A/MAX693A/MAX800L/MAX800M Block Diagram
5.0V
VCC RESET 4.0V THRESHOLD 5.0V 0V 5V 0V CE OUT 15s 100s 5V 0V 5V 0V LOGIC LEVELS SHOWN ARE FROM 0V TO 5V. RESET RESET 100s CE IN
Figure 5. Reset and Chip-Enable Timing
10 ______________________________________________________________________________________
Microprocessor Supervisory Circuits MAX691A/MAX693A/MAX800L/MAX800M
+5V VBATT 2.8V VCC VBATT +5V VCC
MAX691A MAX693A MAX800L MAX800M
CE IN CE OUT GND CLOAD
2.0V to 5.5V
MAX691A MAX693A MAX800L PFO PFI MAX800M
GND
LOW BATT
50 OUTPUT IMPEDANCE
Figure 6. CE Propagation Delay Test Circuit
Figure 7. Low-Battery Indicator
Table 2. Input and Output Status in Battery-Backup Mode
PIN 1 2 3 4 5 6 7 8 9 NAME VBATT VOUT VCC GND BATT ON LOWLINE OSC IN OSC SEL PFI STATUS Supply current is 1A max. VOUT is connected to VBATT through an internal PMOS switch. Battery switchover comparator monitors VCC for active switchover. GND 0V, 0V reference for all signals. Logic high. The open-circuit output is equal to VOUT. Logic low* OSC IN is ignored. OSC SEL is ignored. The power-fail comparator remains active in the battery-backup mode for VCC VBATT - 1.2V typ. The power-fail comparator remains active in the battery-backup mode for VCC VBATT - 1.2V typ. Below this voltage, PFO is forced low. Watchdog is ignored. Logic high. The open-circuit voltage is equal to VOUT. High impedance Logic high. The open-circuit voltage is equal to VOUT. Logic low* High impedance*
Power-Fail Output The Power-Fail Output (PFO) goes low when PFI goes below 1.25V. It typically sinks 3.2mA with a saturation voltage of 0.1V. With PFI above 1.25V, PFO is actively pulled to VOUT.
Battery-Backup Mode
Two conditions are required to switch to battery-backup mode: 1) VCC must be below the reset threshold, and 2) VCC must be below VBATT. Table 2 lists the status of the inputs and outputs in battery-backup mode.
Battery-On Output
The Battery-On (BATT ON) output indicates the status of the internal V CC /battery-switchover comparator, which controls the internal VCC and VBATT switches. For VCC greater than VBATT (ignoring the small hysteresis effect), BATT ON typically sinks 3.2mA at 0.1V saturation voltage. In battery-backup mode, this terminal sources approximately 10A from VOUT. Use BATT ON to indicate battery-switchover status or to supply base drive to an external pass transistor for higher-current applications (see Typical Operating Circuit).
10
PFO
Input Supply Voltage
The Input Supply Voltage (VCC) should be a regulated 5V. VCC connects to VOUT via a parallel diode and a large PMOS switch. The switch carries the entire current load for currents less than 250mA. The parallel diode carries any current in excess of 250mA. Both the switch and the diode have impedances less than 1 each. The maximum continuous current is 250mA, but power-on transients may reach a maximum of 1A.
11 12 13 14 15 16
WDI CE OUT CE IN WDO RESET RESET
* VCC must be below the reset threshold to enter battery-backup mode.
______________________________________________________________________________________ 11
Microprocessor Supervisory Circuits MAX691A/MAX693A/MAX800L/MAX800M
Battery-Backup Input
The Battery-Backup Input (VBATT) is similar to the VCC input except the PMOS switch and parallel diode are much smaller. Accordingly, the on-resistances of the diode and the switch are each approximately 10. Continuous current should be limited to 25mA and peak currents (only during power-up) limited to 250mA. The reverse leakage of this input is less than 1A over temperature and supply voltage (Figure 8). 1) Normal operating mode with all circuitry powered up. Typical supply current from VCC is 35A while only leakage currents flow from the battery. 2) Battery-backup mode where VCC is typically within 0.7V below VBATT. All circuitry is powered up and the supply current from the battery is typically less than 60A. 3) Battery-backup mode where V CC is less than VBATT by at least 0.7V. VBATT supply current is 1A max.
Output Supply Voltage
The Output Supply Voltage (VOUT) pin is internally connected to the substrate of the IC and supplies current to the external system and internal circuitry. All opencircuit outputs will, for example, assume the VOUT voltage in their high states rather than the VCC voltage. At the maximum source current of 250mA, VOUT will typically be 200mV below VCC. Decouple this terminal with a 0.1F capacitor.
Using SuperCap or MaxCap with the MAX691A/MAX693A/MAX800L/MAX800M
VBATT has the same operating voltage range as VCC, and the battery switchover threshold voltages are typically 30mV centered at VBATT, allowing use of a SuperCap and a simple charging circuit as a backup source (Figure 9). If VCC is above the reset threshold and VBATT is 0.5V above VCC, current flows to VOUT and VCC from VBATT until the voltage at VBATT is less than 0.5V above VCC. For example, with a SuperCap connected to VBATT and through a diode to VCC, if VCC quickly changes from 5.4V to 4.9V, the capacitor discharges through VOUT and VCC until VBATT reaches 5.1V typ. Leakage current through the SuperCap charging diode and the internal power diode eventually discharges the SuperCap to VCC. Also, if VCC and VBATT start from 0.1V above the reset threshold and power is lost at VCC, the SuperCap on VBATT discharges through VCC until VBATT reaches the reset threshold; then the battery-backup mode is initiated and the current through VCC goes to zero.
__________Applications Information
The MAX691A/MAX693A/MAX800L/MAX800M are not short-circuit protected. Shorting VOUT to ground, other than power-up transients such as charging a decoupling capacitor, destroys the device. All open-circuit outputs swing between VOUT and GND rather than VCC and GND. If long leads connect to the chip inputs, insure that these leads are free from ringing and other conditions that would forward bias the chip's protection diodes. There are three distinct modes of operation:
+5V 3 VBATT 1N4148 1 VCC
MAX691A MAX693A MAX800L MAX800M
VCC
VBATT
VOUT
2
VOUT 0.1F
0.47F*
MAX691A MAX693A MAX800L MAX800M
GND 4
* MaxCap
Figure 8. VCC and VBATT to VOUT Switch
Figure 9. SuperCap or MaxCap on VBATT
12
______________________________________________________________________________________
Microprocessor Supervisory Circuits MAX691A/MAX693A/MAX800L/MAX800M
Rp* CE VOUT CE IN CE OUT CE CE RAM 1 R1 C1* PFI VCC VIN
+5V
MAX691A MAX693A MAX800L MAX800M
GND
CE
RAM 2 R3 R2
MAX691A MAX693A MAX800L MAX800M
PFO
CE CE RAM 3 TO P CE RAM 4 CE 5V PFO 0V 0V VTRIP = 1.25 R1 + R2 R2
GND *OPTIONAL
VL VTRIP VH VIN
*MAXIMUM Rp VALUE DEPENDS ON THE NUMBER OF RAMS. MINIMUM Rp VALUE IS 1k.
ACTIVE-HIGH CE LINES FROM LOGIC
VH = 1.25/
R2 I I R3 R1 + R2 I I R3
VL - 1.25 + 5 - 1.25 = 1.25 R1 R3 R2
Figure 10. Alternate CE Gating
Figure 11. Adding Hysteresis to the Power-Fail Comparator
If using separate power supplies for VCC and VBATT, VBATT must be less than 0.3V above VCC when VCC is above the reset threshold. As described in the previous section, if VBATT exceeds this limit and power is lost at VCC, current flows continuously from VBATT to VCC via the VBATT-to-VOUT diode and the VOUT-to-VCC switch until the circuit is broken (Figure 8).
Using Separate Power Supplies for VBATT and VCC
+5V R1 VCC PFI PFO
Alternate Chip-Enable Gating
Using memory devices with both CE and CE inputs allows the CE loop to be bypassed. To do this, connect CE IN to ground, pull up CE OUT to VOUT, and - connect CE OUT to the CE input of each memory device (Figure 10). The CE input of each part then connects directly to the chip-select logic, which does not have to be gated.
R2
MAX691A MAX693A MAX800L MAX800M
GND V-
5V PFO 0V
Adding Hysteresis to the Power-Fail Comparator
Hysteresis adds a noise margin to the power-fail comparator and prevents repeated triggering of PFO when VIN is near the power-fail comparator trip point. Figure 11 shows how to add hysteresis to the power-fail com-
5 - 1.25 = 1.25 - VTRIP R1 R2 NOTE: VTRIP IS NEGATIVE.
VTRIP V-
0V
Figure 12. Monitoring a Negative Voltage
13
______________________________________________________________________________________
Microprocessor Supervisory Circuits MAX691A/MAX693A/MAX800L/MAX800M
Backup-Battery Replacement
MAXIMUM TRANSIENT DURATION (s) VCC = 5V TA = +25C 0.1F CAPACITOR FROM VOUT TO GND
MAX791-16
100
80
The backup battery may be disconnected while VCC is above the reset threshold. No precautions are necessary to avoid spurious reset pulses.
Negative-Going VCC Transients
While issuing resets to the P during power-up, powerdown, and brownout conditions, these supervisors are relatively immune to short-duration, negative-going VCC transients (glitches). It is usually undesirable to reset the P when VCC experiences only small glitches. Figure 13 shows maximum transient duration vs. resetcomparator overdrive, for which reset pulses are not generated. The graph was produced using negativegoing VCC pulses, starting at 5V and ending below the reset threshold by the magnitude indicated (reset comparator overdrive). The graph shows the maximum pulse width a negative-going VCC transient may typically have without causing a reset pulse to be issued. As the amplitude of the transient increases (i.e., goes farther below the reset threshold), the maximum allowable pulse width decreases. Typically, a VCC transient that goes 100mV below the reset threshold and lasts for 40s or less will not cause a reset pulse to be issued. A 100nF bypass capacitor mounted close to the VCC pin provides additional transient immunity.
60
40
20 0 10 100 1000 10000 RESET COMPARATOR OVERDRIVE, (Reset Threshold Voltage - VCC) (mV)
Figure 13. Maximum Transient Duration without Causing a Reset Pulse vs. Reset Comparator Overdrive
parator. Select the ratio of R1 and R2 such that PFI sees 1.25V when VIN falls to the desired trip point (VTRIP). Resistor R3 adds hysteresis. It will typically be an order of magnitude greater than R1 or R2. The current through R1 and R2 should be at least 1A to ensure that the 25nA (max) PFI input current does not shift the trip point. R3 should be larger than 10k to prevent it from loading down the PFO pin. Capacitor C1 adds noise rejection.
Connecting a Timing Capacitor at OSC IN
When OSC SEL is connected to ground, OSC IN disconnects from its internal 10A (typ) pullup and is internally connected to a 100nA current source. When a capacitor is connected from OSC IN to ground (to select alternative reset and watchdog timeout periods), the current source charges and discharges the timing capacitor to create the oscillator that controls the reset and watchdog timeout period. To prevent timing errors or oscillator startup problems, minimize external current leakage sources at this pin, and locate the capacitor as close to OSC IN as possible. The sum of PC-board leakage plus OSC capacitor leakage must be small compared to 100nA.
Monitoring a Negative Voltage
The power-fail comparator can be used to monitor a negative supply voltage using Figure 12's circuit. When the negative supply is valid, PFO is low. When the negative supply voltage drops, PFO goes high. This circuit's accuracy is affected by the PFI threshold tolerance, the VCC voltage, and resistors R1 and R2.
14
______________________________________________________________________________________
Microprocessor Supervisory Circuits
Maximum VCC Fall Time
The VCC fall time is limited by the propagation delay of the battery switchover comparator and should not exceed 0.03V/s. A standard rule of thumb for filter capacitance on most regulators is on the order of 100F per amp of current. When the power supply is shut off or the main battery is disconnected, the associated initial VCC fall rate is just the inverse or 1A/100F = 0.01V/s. The VCC fall rate decreases with time as VCC falls exponentially, which more than satisfies the maximum fall-time requirement.
START
MAX691A/MAX693A/MAX800L/MAX800M
SET WDI LOW
Watchdog Software Considerations
A way to help the watchdog timer keep a closer watch on software execution involves setting and resetting the watchdog input at different points in the program, rather than "pulsing" the watchdog input high-low-high or low-high-low. This technique avoids a "stuck" loop where the watchdog timer continues to be reset within the loop, keeping the watchdog from timing out. Figure 14 shows an example flow diagram where the I/O driving the watchdog input is set high at the beginning of the program, set low at the beginning of every subroutine or loop, then set high again when the program returns to the beginning. If the program should "hang" in any subroutine, the I/O is continually set low and the watchdog timer is allowed to time out, causing a reset or interrupt to be issued.
SUBROUTINE OR PROGRAM LOOP SET WDI HIGH
RETURN
END
Figure 14. Watchdog Flow Diagram
______________________________________________________________________________________
15
Microprocessor Supervisory Circuits MAX691A/MAX693A/MAX800L/MAX800M
Ordering Information (continued)
PART MAX691AEJE MAX691AMJE MAX691AMSE/PR MAX691AMSE/PR-T MAX693ACUE MAX693ACSE MAX693ACWE MAX693ACPE MAX693AC/D MAX693AEUE MAX693AESE MAX693AEWE MAX693AEPE MAX693AEJE MAX693AMJE MAX800LCUE MAX800LCSE MAX800LCPE MAX800LEUE MAX800LESE MAX800LEPE MAX800MCUE MAX800MCSE MAX800MCPE MAX800MEUE MAX800MESE MAX800MEPE TEMP RANGE -40C to +85C -55C to +125C -55C to +125C -55C to +125C -0C to +70C -0C to +70C -0C to +70C -0C to +70C -0C to +70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -0C to +70C -0C to +70C -0C to +70C -40C to +85C -40C to +85C -40C to +85C -0C to +70C -0C to +70C -0C to +70C -40C to +85C -40C to +85C -40C to +85C PINPACKAGE 16 CERDIP 16 CERDIP** 16 Wide SO** 16 Wide SO** 16 TSSOP 16 Narrow SO 16 Wide SO 16 Plastic DIP Dice* 16 TSSOP 16 Narrow SO 16 Wide SO 16 Plastic DIP 16 CERDIP 16 CERDIP 16 TSSOP 16 Narrow SO 16 Plastic DIP 16 TSSOP 16 Narrow SO 16 Plastic DIP 16 TSSOP 16 Narrow SO 16 Plastic DIP 16 TSSOP 16 Narrow SO 16 Plastic DIP
PFI PFO OSC IN OSC SEL 0.07" (1.778mm) BATT ON LOW LINE WDI GND VCC WDO CE IN CE OUT 0.11" (2.794mm)
___________________Chip Topography
VOUT VBATT RESET RESET
SUBSTRATE CONNECTED TO VOUT
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 16 TSSOP 16 CERDIP 16 Narrow SO 16 Plastic DIP 16 Wide SO PACKAGE CODE U16-1 J16-3 S16-3 P16-1 W16-1 DOCUMENT NO. 21-0066 21-0045 21-0041 21-0043 21-0042
*Dice are specified at TA = +25C, DC parameters only. **Contact factory for availability and processing to MIL-STD-883B. Devices in PDIP, SO and TSSOP packages are available in both leaded and lead-free packaging. Specify lead free by adding the + symbol at the end of the part number when ordering. Lead free not available for CERDIP package.
16
______________________________________________________________________________________
Microprocessor Supervisory Circuits
Revision History
REVISION NUMBER 0 1 2 3 4 5 6 7 8 9 10 11 REVISION DATE 09/92 12/92 5/93 12/93 3/94 8/94 1/95 12/96 12/99 4/02 11/05 8/08 Initial release Update Electrical Characteristics table. Update Electrical Characteristics table, Tables 1 and 2. Update Electrical Characteristics table. Update Electrical Characteristics table. Correction to Figure 4. Update to new revision and correct errors. Update Electrical Characteristics table. Updated Ordering Information, Pin Configuration, Absolute Maximum Ratings, and Package Information. Corrected Ordering Information. Added lead-free information. Updated Ordering Information. DESCRIPTION PAGES CHANGED -- 2, 3, 4 2, 3, 4, 9, 11 2, 3, 4 2, 3, 4 10 -- 2, 3, 4 1, 2, 16 1 1, 16 1, 16
MAX691A/MAX693A/MAX800L/MAX800M
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17
(c) 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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